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SPARS - Development of Novel System and Component Architectures for Future Innovative 100  GBit/s Communication Systems

Proposer

Prof. Dr.-Ing. Manfred Berroth

Prof. Dr.-Ing. Frank Ellinger

Prof. Dr.-Ing. Martin Vossiek

Prof. Dr.-Ing. Robert Weigel

Abstract

In this project, novel system concepts and components for innovative 100 GBit/s communication systems will be developed. The proposed system architecture is based upon a novel combination of the super-regenerative amplitude demodulator and the recent approach of the pulsed regenerative phase sampling approach. This innovative approach will be established as a very capable low complexity and low power system architecture for ultra-high speed quadrature modulated wireless communication with a data rate of 100 GBit/s at mm-wave frequencies up to 250 GHz. It employs a switched injection-locked oscillator (SILO) as a single stage high gain (> 60 dB) positive feedback amplifier that allows the regeneration of both phase and amplitude of a weak quadrature modulated signal injected into its feedback loop. This concept eliminates long chains of power consuming linear amplifiers when operating close to the transition frequency of current high performance semiconductor technologies. Additionally, it removes the need for high power mm- wave phased-locked loop (PLL) stabilized local oscillator signals: In the transmitter frontend, the mm-wave signal is regenerated from a low power level quadrature modulator output with frequency multiplied microwave local oscillator. In the receiver, two subsequent pulses that were regenerated to a fixed amplitude range are quadrature mixed for demodulation. Consequently, a significant boost in reducing power consumption and system complexity can be expected. In order to provide a profound theoretical framework for this concept, a system theoretic model will be derived, analyzed and simulated. Furthermore, the specific technological boundary conditions of ultra high bandwidth operation up to 250 GHz when reaching the borders of current technology like limited loop gain, noise, switching spurs and their effect on the SILO based combination of amplitude regeneration and phase sampling will be considered particularly. For demonstration, complete transmitter and receiver frontends based on integrated circuits using current high end silicon germanium technology will be implemented. They include 25 GBit/s analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) that are – for the first time – optimized for low power consumption and lower output amplitudes in comparison to state of the art components primarily targeted at optical communications.

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